AI Compute Value-Chain

BASE CASE: Micron/HBM keeps dominating MORE durably than Nvidia on UNIT necessity, but with HIGHER margin VARIANCE than the draft conceded — and value broadly SHIFTS down the stack to the chip-agnostic chokepoints, with EDA/IP (not memory) the single cleanest toll. The dominance RANKING (HBM more chip-agnostic-necessary than Nvidia) stands; the CONFIDENCE on HBM's MARGIN is now correctly bounded by a cyclical-commodity base rate. MICRON/HBM (memory) — anchor RECONCILED, conviction re-bounded. The 24-Jun-2026 FQ3'26 print is REAL and verified against the live filing: record $41.46B rev (+74% sequential off FQ2'26's $23.86B), 84.9% non-GAAP GM, FQ4 guide ~$50B / ~86% GM / $31 EPS, ~$100B RPO across 16 strategic customer agreements, >$1B HBM4 shipped. The critique's BLOCKER — that this contradicts the L6 card — resolves in the draft's FAVOR: the card was STALE (it showed FQ2'26 actuals + an FQ3 estimate of ~$33.5B/81% that the actual print BEAT by a wide margin), not the synthesis hallucinating a P-5 citation. The anchor is sound; I corrected the secondary detail ($22B deposits -> ~$100B RPO / 16 agreements). BUT the critique's substantive point stands and is now built in: HBM/DRAM is the most violently cyclical product in semis, and the honest BASE RATE is mean-reversion — prior up-cycles (2016-18, 2020-21) reverted toward 20-40% GM within ~14-16 months of peak, and Morgan Stanley models 2026 industry median GM down sharply. The 'structural not seasonal' claim is a SUPPLIER claim, not settled fact (the 23-Jun semicap selloff is the live warning; CXMT the named glut trigger). Net: HBM dominance on NECESSITY persists (every accelerator crosses the 3-maker oligopoly; the pool GROWS on both the GPU and ASIC side), but its 70-85% MARGIN is the highest-variance leg in the top tier — hence re-ranked #3 (below EDA and foundry, whose moats are IP/yield-learning not a price cycle) and re-labeled highest-conviction-but-highest-variance rather than cleanly #1. NVIDIA (compute) — dominance more contested, margin slightly UNDERSTATED in the draft. Nvidia keeps the largest gross-profit pool (~$220B/yr) and the category-definer role, but its dominance is the MORE contested of the two and its moat is MIGRATING from the bare chip to the system (NVLink + Spectrum-X networking +199% YoY, CUDA). Correction per the critique: the draft quoted ~74.9% as Nvidia's DC margin, but 74.9%/75% is the BLENDED corporate figure — the DATA-CENTER SEGMENT runs HIGHER (~78%), so the draft slightly understated the defended pool. The honest read: Nvidia's UNIT share at the inference tier is eroding (~95% peak -> ~75-80% by end-2026; custom ASICs ~25% of inference by 2026, growing ~44.6% vs ~16% for merchant GPU), and pricing power is capped — DC GM modeled to re-rate toward ~65-68% by FY2028 (analyst forward modeling, NOT company guidance). Nvidia stays dominant in frontier dense/MoE TRAINING and at the system/networking level; it loses the merchant-GPU pricing PREMIUM at the inference tier. The margin it sheds is captured by own-silicon hyperscalers, partially by Broadcom/Marvell (capped cost-plus), and flows through undiminished to EDA/HBM/packaging/foundry/EUV/networking/optics/power. WHERE VALUE SHIFTS TO: the IP- and physics-bound toll-booths that tax the DESIGN ACT or the wafer/atoms regardless of architecture — EDA/IP (Synopsys/Cadence/Arm, the purest and highest-RATE toll, ~80%+ GM, DIRECTLY tailwinded by more tape-outs), TSMC (foundry, >90% advanced-node, yield-learning moat = lowest variance), HBM (grows on both sides but cyclical-margin), ASML+WFE (EUV monopoly POSITION at a mid-pack 51-53% RATE), CoWoS + ABF substrate (slot/substrate count grows as designers fragment), networking (merchant Ethernet gains as fabric defects from NVLink), optics (InP/DSP chokepoint), and power (generation + electrical gear, the binding constraint). AND to vertically-integrated own-silicon hyperscalers. MAIN WAYS THIS IS WRONG (three failure modes, now including the dema…