State of AI Compute
Margin-Pool Migration under Custom-Silicon Proliferation
Buy the moat, not the multiple.
Durable margin migrates down + around the chip-design layers to chip-agnostic toll-booths (EDA/IP, foundry, HBM, EUV) + own-silicon hyperscalers — away from the merchant-GPU premium and the GPU-rental spread. At 25-Jun prices almost everything is a wonderful business at a peak-cycle multiple, so the disciplined book is mostly hedged/paired/waiting.
BASE CASE: Micron/HBM keeps dominating MORE durably than Nvidia on UNIT necessity, but with HIGHER margin VARIANCE than the draft conceded — and value broadly SHIFTS down the stack to the chip-agnostic chokepoints, with EDA/IP (not memory) the single cleanest toll. The dominance RANKING (HBM more chip-agnostic-necessary than Nvidia) stands; the CONFIDENCE on HBM's MARGIN is now correctly bounded by a cyclical-commodity base rate. MICRON/HBM (memory) — anchor RECONCILED, conviction re-bounded. The 24-Jun-2026 FQ3'26 print is REAL and verified against the live filing: record $41.46B rev (+74% sequential off FQ2'26's $23.86B), 84.9% non-GAAP GM, FQ4 guide ~$50B / ~86% GM / $31 EPS, ~$100B RPO across 16 strategic customer agreements, >$1B HBM4 shipped. The critique's BLOCKER — that this contradicts the L6 card — resolves in the draft's FAVOR: the card was STALE (it showed FQ2'26 actuals + an FQ3 estimate of ~$33.5B/81% that the actual print BEAT by a wide margin), not the synthesis hallucinating a P-5 citation. The anchor is sound; I corrected the secondary detail ($22B deposits -> ~$100B RPO / 16 agreements). BUT the critique's substantive point stands and is now built in: HBM/DRAM is the most violently cyclical product in semis, and the honest BASE RATE is mean-reversion — prior up-cycles (2016-18, 2020-21) reverted toward 20-40% GM within ~14-16 months of peak, and Morgan Stanley models 2026 industry median GM down sharply. The 'structural not seasonal' claim is a SUPPLIER claim, not settled fact (the 23-Jun semicap selloff is the live warning; CXMT the named glut trigger). Net: HBM dominance on NECESSITY persists (every accelerator crosses the 3-maker oligopoly; the pool GROWS on both the GPU and ASIC side), but its 70-85% MARGIN is the highest-variance leg in the top tier — hence re-ranked #3 (below EDA and foundry, whose moats are IP/yield-learning not a price cycle) and re-labeled highest-conviction-but-highest-variance rather than cleanly #1. NVIDIA (compute) — dominance more contested, margin slightly UNDERSTATED in the draft. Nvidia keeps the largest gross-profit pool (~$220B/yr) and the category-definer role, but its dominance is the MORE contested of the two and its moat is MIGRATING from the bare chip to the system (NVLink + Spectrum-X networking +199% YoY, CUDA). Correction per the critique: the draft quoted ~74.9% as Nvidia's DC margin, but 74.9%/75% is the BLENDED corporate figure — the DATA-CENTER SEGMENT runs HIGHER (~78%), so the draft slightly understated the defended pool. The honest read: Nvidia's UNIT share at the inference tier is eroding (~95% peak -> ~75-80% by end-2026; custom ASICs ~25% of inference by 2026, growing ~44.6% vs ~16% for merchant GPU), and pricing power is capped — DC GM modeled to re-rate toward ~65-68% by FY2028 (analyst forward modeling, NOT company guidance). Nvidia stays dominant in frontier dense/MoE TRAINING and at the system/networking level; it loses the merchant-GPU pricing PREMIUM at the inference tier. The margin it sheds is captured by own-silicon hyperscalers, partially by Broadcom/Marvell (capped cost-plus), and flows through undiminished to EDA/HBM/packaging/foundry/EUV/networking/optics/power. WHERE VALUE SHIFTS TO: the IP- and physics-bound toll-booths that tax the DESIGN ACT or the wafer/atoms regardless of architecture — EDA/IP (Synopsys/Cadence/Arm, the purest and highest-RATE toll, ~80%+ GM, DIRECTLY tailwinded by more tape-outs), TSMC (foundry, >90% advanced-node, yield-learning moat = lowest variance), HBM (grows on both sides but cyclical-margin), ASML+WFE (EUV monopoly POSITION at a mid-pack 51-53% RATE), CoWoS + ABF substrate (slot/substrate count grows as designers fragment), networking (merchant Ethernet gains as fabric defects from NVLink), optics (InP/DSP chokepoint), and power (generation + electrical gear, the binding constraint). AND to vertically-integrated own-silicon hyperscalers. MAIN WAYS THIS IS WRONG (three failure modes, now including the dema…
Full-stack value chain
Thirteen toll-booth layers from demand (the model cos) down to physics (grid power). The marker shows where custom-silicon proliferation is a tailwind, headwind, or mixed for each layer’s margin pool. Tap any layer for the full read.
The deep physics toll-booths — HBM, packaging, fab, optics, power — get stronger as custom silicon proliferates. Every chip, whoever designs it, must still cross them.
Shift-point register
Ranked by margin-at-stake × demand-durability × evidence-strength. The flagged rows clear the bar and are promoted to a deep-dive.
EDA + foundational IP
EDA + foundational IP: the purest chip-agnostic toll that custom-silicon proliferation directly tailwinds
Every leading-edge design — merchant GPU OR custom ASIC — is architected, simulated, verified, and signed off inside Synopsys/Cadence tooling on top of Arm (or licensed RISC-V) core IP and third-party PHY/SerDes/memory-controller IP. There is no route around it: you cannot tape out a 2nm part without EDA + IP, and the duopoly (Synopsys+Cadence ~70%+ of EDA) plus Arm's instruction-set lock-in make it the most defensible position in the stack at ~80%+ software gross margins. The custom-silicon shift is a DIRECT, super-linear tailwind: more bespoke designs = more tape-outs = more tool seats, more IP-royalty-bearing chips, more verification compute. The toll is levied on the design act itself, upstream of every wafer.
Opportunity board
31 names sorted into three buckets — durable compounders, undervalued / high-potential, and short / avoid. Each tile shows its conviction; open one for the thesis, catalyst, and falsifier.
Durable compounder
12Undervalued / high-potential
13Short / avoid
6Views & the Voices
The strongest bull and the strongest bear case, the US-listed ETF expressions of the theme, and where the tracked QAI Voices roster nets out — each stance stamped trackable vs inferred.
Bull case
the longBuy the moat, not the multiple: the durable margin in the AI compute value chain sits in the chip-agnostic toll-booths -- EDA/IP (Synopsys+Cadence ~85% of EDA), foundry (TSMC ~44% Foundry-2.0 share, 66% gross margin), HBM (3-player oligopoly, sold out through 2026), and the EUV monopoly (ASML, ~100% of EUV) -- plus the own-silicon hyperscalers who internalize the GPU margin. The central insight: custom-silicon proliferation, which threatens Nvidia's 75% GPU margin, is BULLISH for the toll-booths. Every TPU, Trainium, Maia and MTIA still needs Synopsys/Cadence to design it, TSMC to fab it, ASML's EUV to pattern it, and SK Hynix/Micron HBM to feed it. The fight over who sells the accelerator is a fight Nvidia can lose while the toll-booths win on every unit shipped -- they monetize 'AI compute grows' without betting on which architecture wins. [estimate] Vintage: Q1-Q2 2026 prints. Not financial advice.
- FOUNDRY -- TSMC is the un-disintermediable chokepoint and prices like one. Q1 2026 gross margin hit a record 66.2% with advanced nodes (3nm+5nm) at 61% of wafer revenue and HPC/AI at 61% of total revenue; CEO guided >30% full-year growth; IDC puts TSMC at ~44% of a >$360B Foundry-2.0 market [fact, Q1 2026]. Every leading-edge accelerator -- Nvidia, AMD, every hyperscaler ASIC, Broadcom/Marvell co-designs -- taped out on N3/N2 through TSMC; Apple pre-booked >half of initial 2nm capacity. Custom silicon ADDS TSMC customers rather than subtracting them: TSMC is architecture-agnostic and captures the wafer no matter who wins the chip war [analysis].
- EUV -- ASML is a ~100% monopoly on the one tool no advanced chip can skip. Q1 2026 revenue EUR 8.8B, FY guidance raised to EUR 36-40B, backlog ~EUR 38.8B (~a full year), EUV ~65% of system sales; High-NA units sell at 2-3x a standard EUV [fact, Q1 2026]. No second EUV supplier exists or is buildable on a relevant horizon (Nikon/Canon do not make EUV). More nodes, more designs, more re-spins from the ASIC boom = more EUV layers per wafer = more ASML, regardless of architecture winner [analysis].
- EDA/IP -- the purest architecture-agnostic toll. Synopsys + Cadence hold ~85% of EDA; every modern processor from Nvidia/AMD/Broadcom/Apple AND every hyperscaler ASIC is designed on their tools, on sticky multi-year subscription + reusable IP [fact, 2026]. The MORE designers fragment into custom silicon, the MORE seats and IP cores sold -- they sell shovels in every gold rush and literally cannot be on the losing side of the chip war. Synopsys closed the $35B Ansys deal (multiphysics moat-widening); Arm AGI CPU runs on their full stack [fact].
Bear case
the short / avoidThe strongest short/avoid is not 'AI is fake' -- it is that the ENTIRE compute value chain is one correlated, capex-funded bet whose unit economics do not yet close, and that even the moated toll-booths are late-cycle cyclicals being priced as secular monopolies. ~$500-527B of 2026 AI capex is chasing ~$50-60B of AI revenue (~$8-10 of spend per $1 of revenue), much of it circular (Nvidia funds OpenAI which buys Nvidia; OpenAI projects $14B of 2026 losses) [fact/estimate, 2026]. The toll-booths' record margins -- TSMC 66%, HBM sold-out, ASML full backlog -- are PEAK-cycle prints that the market is extrapolating; memory is the most violently mean-reverting business in tech and every prior memory supercycle has ended the same way. Layer on a hard physical ceiling (power/grid: Gartner sees 40% of AI datacenters power-constrained by 2027) and a single-point-of-failure (Taiwan), and the chain is a high-beta bet on infinite, profitable AI demand that has not been demonstrated. The moat protects you from competitors, not from the cycle. [analysis] Vintage: Q1-Q2 2026. Not financial advice.
- THE CAPEX-REVENUE GAP IS THE WHOLE TRADE. 2026 AI capex revised to ~$527B (Goldman) against ~$50-60B of total AI revenue -- ~$8-10 spent per $1 earned -- with structurally circular financing (Nvidia's $100B to OpenAI largely returns as Nvidia purchases; $300B OpenAI-Oracle; OpenAI guiding $14B 2026 losses) [fact/estimate, 2026]. The toll-booths' backlogs ARE this capex. If hyperscaler ROI disappoints and capex is cut even 20-30%, every moat in the chain de-rates simultaneously -- the diversification is illusory because all eight segments are levered to the same demand input.
- MEMORY/HBM IS A CYCLICAL WEARING A SECULAR COSTUME. 'Sold out through 2026' and 'prices doubled' are the textbook TOP of a memory cycle, not a new paradigm. HBM is racing to ~25% of DRAM wafers; analysts already flag a realistic 2028-2029 oversupply if AI demand moderates as new fabs ramp [estimate, 2026]. Three players expanding into the same sold-out signal is exactly how every glut is seeded. The DRAM price doubling also cannibalizes the broader market (smartphone -12.9%, PC -11.3% shipments) -- demand destruction that historically precedes the down-leg [fact].
- POWER IS THE HARD CEILING THAT SILICON CANNOT BUY THROUGH. Gartner: power shortages restrict 40% of AI datacenters by 2027; ~two-thirds of 2026's announced US AI capacity is not on track to energize; high-power transformer lead times stretched from ~24-30 months to ~5 years; <10GW/yr of new US gas in 2026-2027 [fact/estimate, 2026]. If GPUs/ASICs ship but cannot be powered and racked, wafer/HBM/EUV pull-through stalls regardless of how good the silicon moat is -- value migrates to turbines, transformers and utilities that the 'buy the toll-booth' thesis does not own. The bottleneck has left the chip.
Net bullish on the AI compute value chain, with the strongest conviction NOT on the GPU brand but on the physical chokepoints — TSMC/EUV/WFE (foundry + equipment), HBM/DRAM memory, advanced packaging, and AI-networking/optics — where durable margin is seen migrating as custom-silicon proliferates alongside (not instead of) Nvidia. The dominant frame is 'own the supply chain and power, not just Nvidia' (Laffont's Coatue rotation is the cleanest expression). Memory specialists (Aasholm, Castellano, O'Laughlin) are the most emphatic that a structural re-rate is underway (memory margins >80%, HBM 'breaking the cycle'). Optics/networking voices (Genovese, Roy) see the interconnect layer winning regardless of GPU-vs-ASIC. The custom-silicon question splits the analysts: sell-side/fund bulls (Rasgon, Ferragu, Baker, Kacher) treat ASICs as additive and Nvidia's moat durable, while the grounded skeptics (Goldberg, Lyons, EnerTuition) argue ASIC economics are conditional/workload-specific and switch-silicon margin (Broadcom 2027) may be overpriced.
Dispersion: Moderate. Near-unanimous bullishness on the buildout's magnitude and on memory/packaging/optics as margin pools; the real dispersion is (1) GPU-vs-ASIC margin split — bulls say additive, skeptics say custom silicon is near a 'high-water mark' and Broadcom's 2027 forecast is at risk; and (2) the lone structural bear (Chanos) attacks the whole thesis at the depreciation/financing layer, arguing fast GPU obsolescence and neocloud leverage erode the extrapolated margins. Memory 'this-time-is-different' also has named dissenters on the roster not selected here (Handy, Irrational Analysis) who insist DRAM stays a commodity.
Selection skewed toward the value-chain-relevant subset (semis/foundry, HBM/memory, packaging, EUV, networking, optics, power) and excludes the space/launch and pure-power-grid voices as off-topic for the custom-silicon-margin-migration question. Trackable = reconstructable from a published note or 13F (the fund holders Laffont/Kacher/Baker, and the named-published independents Patel/O'Laughlin/Aasholm/Castellano/Goldberg/Lyons); inferred = stance assembled from TV/podcast/paywalled commentary without a single reconstructable position (Rasgon, Ferragu, Genovese, Roy, EnerTuition, Chanos) — these are characterizations, NOT confirmed verbatim quotes. Vintages are 2025-12 to 2026-Q2; Ferragu's only public hard rating action (a 2024 Nvidia downgrade) is stale and superseded by the 2026 Best-Idea bull note. Not financial advice.
US-listed ETF expressions
15The QAI Voices
stance · trackable / inferredPrediction matrix
Directional calls across Sep'26 / Dec'26 / Jun'27 / Jun'28, confidence decaying high → low over the horizon. Each cell is the call; click a row for the full reasoning, leading indicator, and falsifier.
Reference date 25 Jun 2026, $10M paper book. The AI-compute value chain splits into durable tolls (process-control, EUV, EDA, foundry-node, custom-XPU/networking) priced near 47-60x forward, and cyclical peak-margin names (HBM/NAND/DRAM, neocloud) priced cheap on peak EPS. THE DOMINANT NEAR-TERM RISK across every horizon is the same single factor — a hyperscaler AI-capex air-pocket — which fires every long's falsifier simultaneously, so the matrix's category calls are highly correlated and the diversification is illusory. 3mo (Sep'26): momentum-extended tape, most names within ~8% of ATHs; the dispersion event is the Jun-Aug print cycle (MU already beat, SK Hynix/TSMC/AMAT/Eaton/ASML Q2 prints land). Confidence HIGH on direction-of-prints (demand still tight, HBM sold out, WFE guides raised) but the marginal-buyer is paying peak multiples, so price ≠ fundamentals — call is "grind/up on confirming prints, sharp air-pocket-driven drawdown is the binary." 6mo (Dec'26): the memory cycle's second-derivative is the swing — NAND contract prices already decelerating (SNDK), CXMT/YMTC 2027 supply wave looming, HBM4/Rubin timing the bull/bear fork for SK Hynix+Micron. EDA/process-control/EUV tolls keep compounding but the easy re-rate is spent. 1y (Jun'27): the regime question resolves — either the super-cycle extends (N2 sold out into 2028, HBM4 ramps clean, FY27 capex holds >$1T) and tolls re-rate toward monopoly-infra multiples, OR the air-pocket hits and the whole complex de-rates 25-40% on multiple compression (not earnings collapse for the tolls; earnings AND multiple for memory/neocloud). 2y (Jun'28): confidence DECAYS sharply — inference-share migration (UALink/MI400/Ethernet-scale-up vs NVLink, CUDA-portability) and Nvidia GM-fade become the structural story; CoreWeave refinancing cliffs resolve; glass-core/CPO/hybrid-bonding optionality strikes or expires. The honest 2y call is WIDE: the durable tolls (KLAC/ASML/CDNS/SNPS/TSM/AVGO) most likely still standing and compounding, the cyclicals (memory/NAND) past at least one down-leg, Nvidia's margin premium partly competed away, and the leveraged neocloud the canary that either self-funded or broke. Net stance: own the tolls on weakness, size memory/NAND for the roll not the wedding, hold CRWV as a defined-risk put-spread hedge, stay flat ARM/FN/SNDK on valuation. Confidence is high at 3mo (print-driven, observable), medium at 6mo-1y (cycle-timing-dependent), low at 2y (structural-migration-dependent, multiple-regime-dependent).
Valuation scenarios
Every target is scenario-conditional with a probability; the verify produced zero outright buys. Tap a name for its full bull / base / bear ladder.
Regime calls
The four cross-cutting forces and when each bites across the Sep'26 → Jun'28 horizon. Tap any force or modulating risk to read the full call.
Memory Cycle Roll
The HBM/DRAM up-cycle most likely holds through Sep'26 (HBM4/Rubin sold-out book, MU Q3 beat, SK Hynix 70% Rubin allocation) but the second-derivative rolls over late-2026 to 1H27 — NAND leads (contract-price deceleration ALREADY printing per TrendForce/SNDK), DRAM/HBM follows as CXMT/YMTC 2027 supply wave + HBM4-yield-freed wafers return commodity bits. Base case: graceful normalization, not a cliff (contract backlogs cushion), with through-cycle GM re-anchoring (80%→40-50% NAND, 72%→30-40% DRAM blend) the dominant 1y price driver for MU/SNDK/000660.KS. Bear (~30%): Rubin delay + CXMT DDR5 yield-parity floods commodity = violent mean-reversion. WATCH: NAND/DRAM contract-price 2nd derivative (TrendForce Q3/Q4'26), CXMT DDR5 yield-parity timing, Nvidia HBM4 allocation prints.
AI
THE SINGLE CORRELATED FACTOR: Risk is LOW-to-moderate through Sep'26 (FY26 hyperscaler capex ~$725B tracking, orders still >100% YoY at Eaton/backlogs intact), RISES into the FY27 capex-guide season (late-2026/early-2027 — the >$1T FY27 trajectory is where ≥2 of MSFT/GOOGL/META/AMZN cutting >15% is the cross-book falsifier), PEAKS as the binding regime risk over the 6-18mo window. This factor fires nearly every long's falsifier at once (KLAC process-control -10%, ETN orders flip negative, AVGO hyperscaler pause, NVDA/TSM/ASML capex-pause, CRWV utilization/refi) — so the book's real independent risk is far below gross. The disciplined expression across all verdicts: a portfolio-level AI-capex factor budget, not name-by-name sizing. WATCH: the four hyperscalers' FY27 capex guides (the leading indicator that pre-dates toll-booth income-statement weakness), Eaton Electrical Americas rolling-12mo orders, CoreWeave book-to-bill/utilization (the canary that leads).
Inference
A 2H27-2028 STORY, NOT 2026: Nvidia's ~75% GM and multiple premium are defended through 2027-28 by NVLink rack-scale + CoWoS supply-lock + CUDA-inference inertia; the falsifier (first GM-fade print <60%, OR UALink reaching volume scale-up AND MI400/Helios taking credible hyperscaler share AND production inference porting off CUDA at scale) is a 2027-28 window event. CAUTION (per the NVDA red-team): the Broadcom-Tomahawk merchant-Ethernet scale-up route arrives INSIDE the hold window and weakens the UALink-only moat-pillar framing — so the AVGO networking leg is the early beneficiary and the leading tell. The ~10x/yr inference-efficiency compression is volume-expanding (good for total tokens/units) but margin-arbitraging (compresses per-unit pricing power) — net it lengthens demand duration while capping the margin-durability premium. WATCH: Nvidia non-GAAP GM print trajectory (Q2/Q3 FY27), UALink/Ethernet-scale-up production shipments, AVGO merchant-AI-Ethernet attach rate, any flagship lab porting production inference off CUDA.
Multiple
The entire complex trades at peak-cycle multiples on peak-cycle margins near ATHs — the dominant 1-2y drawdown mechanism is MULTIPLE compression (for the tolls: 47-50x→30-33x semicap de-rate; for memory/neocloud: multiple AND earnings). Circular AI-capex financing (Nvidia→neocloud→Nvidia loops, CRWV's $25B debt + GPU-collateral depreciation refinancing cliffs) is the amplifier that converts a capex-deceleration into a forced-deleveraging event. CoreWeave is the canary — its book-to-bill/utilization/refi-pricing leads the toll-booth income statements by 1-2 quarters. WATCH: CRWV 2026 maturity refi coupon, GPU-collateral covenant-headroom disclosures, semicap forward-multiple compression as the de-rate tell, hyperscaler capex-financing structure disclosures.
How they modulate the book
CXMT / China memory glut
CXMT is the explicit glut-trigger for the memory-storage and HBM theses and the verify materially sharpened it: CXMT posted ~70% OPERATING margin on commodity DRAM in 1Q26 — it is NOT a subsidized loss-maker dabbling, it is a proven margin-positive flooder with maximum incentive to add commodity bits fast (capacity ~350 kwspm end-2026, near Micron's ~385), and its DDR5 is already in retail modules. This breaks the COMMODITY-DRAM leg of the two-sided tightness (the shorter ~1.5-2yr, weaker half of the moat) earlier and more economically-motivated than the deep-dive's measured 'soft-landing' tone admits — a direct nearer-term downgrade to MU/SK Hynix/SanDisk/Kioxia sizing. It is a 3-5yr discipline-breaker at the commodity/legacy tier (where even DDR2 is +60%), export-control-gated out of EUV so a ~2028 HBM threat at best. Net: CXMT is a real-yield-uncertainty (claimed ~80% vs skeptic 10-20%) swing variable that turns a soft memory landing into a hard glut; treat any memory long as a DATED cyclical rent that must survive a 20-30% hard-glut GM trough, not a structural re-rate.
Inference-efficiency compression (~10x/yr)
The ~10x/yr per-token inference-cost decline is the single demand-side risk that hits EVERY toll-booth at once — it is the mechanism behind the nvidia-moat inference-commoditization thesis (bare-GPU inference ceding to hyperscaler ASICs) AND the upstream pull-through for foundry/HBM/memory/networking/optics/power. The asymmetry the whole opportunity set rests on: efficiency gains have historically EXPANDED total inference demand (Jevons), so the toll-booths can keep compounding on VOLUME even as per-unit margin compresses — but this is a bet on demand elasticity, not a moat. It cuts hardest at the names priced for both peak margin AND peak volume (LITE, ALAB, BESI, VRT at nosebleed multiples; NVDA at a 68%-floor assumption). It modulates the opportunity set toward the EARLIEST, lowest-cyclicality, design-layer tolls (EDA/IP, KLA process-control, ASML EUV — paid at design, budget-bound, decoupled from the fab capacity cycle) and AWAY from the merchant-margin names whose pricing umbrella the efficiency curve directly arbitrages down.
Neocloud short (the hedge / canary)
The CoreWeave-debt-cliff-vs-Nebius neocloud GPU-landlord short is the cleanest expression of the demand-quality risk that sits UNDER the entire long basket: the GPU-landlord layer is the most leveraged, least-moated, most circular-financing-exposed link, and a neocloud stress event is the leading indicator that the hyperscaler-capex air-pocket (the #1 high-severity risk across foundry, HBM, memory, ASIC, networking, optics, power) has begun. It is a HEDGE, not a core long-side position — pairing a neocloud short against the durable-toll longs (TSM/AVGO/KLA) isolates the structural-margin thesis from the cyclical-demand bet. It is the canary: a CoreWeave debt event or neocloud funding pullback shows up in book-to-bill (VRT, BESI, ASMPT, Arista) and lead-times (TSMC N2, CoWoS) one-to-two quarters before it shows in any toll-booth income statement.
Circular AI-capex financing
Circular AI-capex financing (Nvidia/MSFT/Oracle investing in OpenAI which then buys their compute; Nvidia's $2B into Marvell co-opting it into NVLink-Fusion; Nvidia's 9%-style strategic stakes) is the structural fragility that makes the 'demand exceeds supply' / 'sold out into 2028' / 'book-to-bill ~3x' signatures across foundry, HBM, ASIC, networking and power LESS durable than they look — order books backed by circular financing are cancellable in a confidence shock, and the same vendor cannot both throttle a bottleneck AND guide its dependents' revenue up (the internal inconsistency the ASIC and nvidia-moat verifies caught: the CoWoS/HBM bottleneck cannot be bullish for both NVDA pricing AND AVGO's >$100B realization). It modulates the set by demanding that every 'binding bottleneck' be re-underwritten as budget-/confidence-bound demand, not capacity scarcity — and it specifically caps how much of Marvell's, the neoclouds', and the OpenAI-adjacent supply chain's growth is independent vs vassal/circular. Treat circular-financing exposure as a sizing haircut applied across the whole basket, heaviest on the GPU-landlord and custom-XPU layers.
Premise pressure-test
The six named 2026-Q3 catalysts the thesis rests on, probability-weighted. Click any premise for the if-true / if-false split.
Micron released a strong financial report
confirmedCerebras financial report did not meet expectations
partially confirmedAnthropic is expected to produce its own chips.
partially confirmedAmazon, Google, Microsoft
partially confirmedSpaceX has a space data-center narrative
confirmedTerafab is a new chip/foundry company.
partially confirmed