State of the Memory Supercycle
HBM/DRAM/NAND pricing and the cycle 2nd-derivative, the HBM oligopoly, the CXMT glut trigger, and the through-cycle margin floor — size the rent for the roll, not the wedding.
Size the rent for the roll, not the wedding: own the through-cycle memory winners (MU + WFE toll-booths AMAT/LRCX/KLA, ASML via ADR) at cycle-aware entries; treat the China commodity-DRAM glut (CXMT) as the live falsifier, not a tail.
The HBM oligopoly is real, sold out through 2026, and printing 70%+ memory-division operating margins (SK Hynix 72%, Samsung ~73% est., Micron 74.9% GM Q2-FY26) — the most violent up-leg the industry has seen, with a Goldman-pegged ~4.9% DRAM supply gap, the worst in 15 years. But DRAM/NAND remain the most mean-reverting businesses in tech: the same sold-out-record-price euphoria has historically sat near the cycle top. The durable rent is the WFE toll-booth at the bottom (every memory bit needs AMAT/LRCX/KLA/ASML capacity, gated by 12-month EUV lead times and a €38.8B ASML backlog) and the one US-listed pure memory maker (MU) bought cycle-aware, not the Korea makers at peak multiples — with CXMT's ~350kwspm 2026 DDR5 exit and YMTC NAND as the explicit glut-trigger falsifier to monitor, not dismiss.
Two distinct dominators. On pricing power TODAY: the 3-maker HBM oligopoly — SK Hynix (~62% HBM share, first to High-NA EUV in DRAM), Samsung (~17%), Micron (~21%) — sets memory prices and is capturing all-time-record margins, but this dominance is cyclical and partly an artifact of disciplined capacity restraint (SK Hynix is deliberately slowing HBM4 to keep DRAM tight). On structural durability: the WFE toll-booths (AMAT/LRCX/KLA + ASML's EUV monopoly, ENTG/MKSI materials, Camtek/Onto HBM inspection) — a tighter, more defensible oligopoly than the makers, gated by 12-month+ lead times, a €38.8B ASML backlog, and decades of process IP. The makers' dominance survives only until the next glut; the toll-booths' survives the glut because down-cycle capex cuts hit them later and leading-edge/HBM/High-NA migration keeps WFE intensity rising even as bit growth slows. The most durable rent is the toll-booth (and ASML's EUV monopoly above it), not the maker.
Full-stack value chain
The memory value chain from AI/HBM end-demand down to the wafer-fab equipment and materials that gate supply. The marker shows where the HBM-led supercycle is a tailwind, headwind, or mixed for each layer’s margin pool. Tap any layer for the full read.
The toll-booths that gate memory supply — HBM packaging/TSV, the WFE makers, the 3-maker DRAM oligopoly — defend margin through the cycle, while commodity DRAM and NAND mean-revert. Own the rent; size for the roll.
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Opportunity board
21 names sorted into three buckets — durable compounders, undervalued / high-potential, and short / avoid. Each tile shows its conviction; open one for the thesis, catalyst, and falsifier.
Durable compounder
8Undervalued / high-potential
11Short / avoid
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Full board analytics
The prediction matrix, scenario bands, regime timeline, book construction, premise tests and the shift-point register — the deep analytical layer behind this board.
- Prediction matrix & scenario bands
- Book construction & sizing
- Premise tests & falsifiers
- Shift-point register