Alchip Technologies
Design-services + turnkey: earns NRE (non-recurring engineering) design revenue up front, then higher-volume, lower-margin mass-production/turnkey revenue as customer chips ramp. Asset-light fabless model; manufacturing outsourced to TSMC foundry and OSAT partners. Revenue is lumpy, gated by individual customer product generations.
Earnings, margins, COGS & capex
FY2025 was an explicit down year: revenue fell 38% to $992M from a $1.6B FY2024 peak as production shipments were light and a key customer skipped a product generation. Profitability held up far better than revenue - net income only -11% to $179.4M (from $200.8M) - because gross margin rose to 26% (from 20%) on a richer NRE/design mix. Q1 2026 revenue troughed at $132.4M (-58% YoY) yet net income rose 1.6% YoY to $45.1M on >50% gross margin, an NRE-heavy quarter. Management frames 2025 as a 'hiccup' and guides to a strong H2 2026 as 3nm AI-accelerator production ramps, with 2026 revenue weighted heavily to H2 and consensus pointing back above the 2024 peak.
Income statement — where each revenue dollar goes
% of revenueOf every $1 of revenue, ~74¢ is cost of goods and ~10¢ operating expense, leaving ~16¢ of operating profit (~18¢ net).
Revenue trend
Margins
up from 20% FY2024; >50% in NRE-heavy Q1 2026 - blended margin swings with NRE-vs-production mix
margin up from ~13% FY2024 ($202.3M on $1.6B) even as op-income dollars fell to $161M from $202.3M on the lower revenue base
held up vs revenue drop on richer design mix (net income -11% vs revenue -38%)
down from NT$81.3 FY2024; consensus ~NT$135 for FY2026E (net income +~96%)
COGS structure
Dominated by outsourced wafer (TSMC) and packaging/test (OSAT) costs passed through in turnkey/mass-production revenue - the structural reason blended gross margin sits in the mid-20s% despite design-services NRE carrying >50% margins. Production-heavy quarters dilute margin; NRE-heavy quarters (like Q1 2026) lift it.
Capex
Fabless/asset-light - no fabs; capital needs are design tools (EDA), IP, engineering headcount and test infrastructure. Specific capex not broken out in releases.
Latest earnings
Revenue at cyclical trough (-58% YoY) but gross margin >50% 'exceeded expectations'; net income +1.6% YoY (pre-tax profit +3.5% YoY to $56.4M) - profit resilience beat the revenue optics
No hard full-year revenue number from management, but qualitative: Q2 momentum strengthens, 'very strong' QoQ revenue+profit growth from Q3, 2026 revenue weighted heavily toward H2, driven by North American 3nm AI-accelerator shipments plus strong NRE from an anticipated 2nm accelerator tape-out by year-end. Consensus ~NT$71.3B revenue / ~NT$135 EPS for FY2026; consensus price target ~NT$4,475.
- Q1 2026 revenue
- $132.4M
- Q1 2026 net income
- $45.1M (+1.6% YoY)
- Q1 2026 gross margin
- >50%
- 3nm/2nm share of Q1 2026 revenue
- 21%
- 7nm/5nm share (Q1 2026)
- 63%
- North America revenue (FY2025)
- 78%
- AI/HPC share of revenue (FY2025)
- 83%
Growth drivers
- 3nm AI-accelerator production programs ramping into H2 2026 (North American demand)
- 2nm accelerator tape-out expected by year-end 2026 (next design-win generation)
- Secular growth in hyperscaler/AI custom silicon (in-house accelerators displacing merchant GPUs)
- NRE design-win pipeline converting to high-volume turnkey production
- Advanced-packaging (2.5D/3D, CoWoS-class) large-die HPC designs
Bull & bear
A leveraged, pure-play way to own the hyperscaler custom-silicon supercycle on TSMC's bleeding edge: 2025 was a trough, and 3nm production plus 2nm tape-outs set up a sharp H2 2026 re-acceleration back above the prior peak, with margin upside from design mix.
- FY2026 consensus points to revenue back above the $1.6B FY2024 peak (~NT$71.3B) and net income up ~96%, with EPS ~NT$135
- 2026 revenue is guided heavily H2-weighted - the trough is Q1 2026 and the ramp is visible, not speculative
- Gross margin >50% in NRE-heavy quarters shows real pricing power on the design side; production ramp adds absolute profit dollars
- Established 2nm/3nm large-die execution is a scarce capability - few houses can tape out HPC-class accelerators on the leading node
- 83% AI/HPC exposure and 78% North America (FY2025) aligns the book to the best-funded, fastest-growing silicon demand
Extreme customer concentration and revenue lumpiness make Alchip a boom-bust design house dressed as a secular AI winner - one delayed or lost program can halve revenue (as 2025 showed), margins are structurally thin, and the stock is priced for a flawless ramp against far bigger rivals.
- FY2025 revenue fell 38% because one key customer skipped a generation - that single-point fragility is unresolved and undisclosed
- Blended gross margin ~26% reflects heavy foundry/OSAT pass-through; the business is lower-quality than the >50% NRE quarters imply
- Broadcom and Marvell dominate the largest hyperscaler custom-ASIC programs; TSMC-affiliated GUC competes directly in Taiwan
- US export controls have removed/constrained China-linked HPC demand, a structural headwind to the addressable market
- ~$11B market cap on $992M FY2025 revenue (~11x sales, ~61x trailing EPS) demands the H2-2026 ramp lands on time and consensus NT$135 EPS is hit
- Dependence on TSMC CoWoS-class packaging allocation caps how fast production can actually scale regardless of design wins
What it is worth
Sales/earnings multiple, cross-checked against the cyclical trough and consensus recovery
Ramp slips a quarter or a key program moves/insources; revenue re-airpockets like 2025, the ~11x-sales / high-P/E premium compresses sharply, and the stock de-rates well below $11B.
Recovery largely as guided (H2-weighted, consensus met); stock holds ~$11B as the forward multiple normalizes into delivered growth - value migrates from multiple to earnings.
Ramp executes and the customer base broadens: FY2026 revenue back above the $1.6B peak with EPS ~NT$135+, forward P/E ~31x re-rates higher on a multi-year 2nm cycle - meaningful upside from ~$11B.
~$10.8B market cap on FY2025 revenue of $992M is ~11x trailing sales and a rich earnings multiple (FY2025 EPS NT$69.2 vs ~NT$4,215 price = ~61x trailing; stockanalysis PE ~63x) - the stock discounts the H2-2026 recovery, not the trailing trough. On consensus FY2026E (~NT$71.3B revenue, ~NT$135 EPS, net income ~+96%) the forward P/E compresses toward ~31x. The multiple is only supportable if the H2 ramp lands on time and the single-customer concentration doesn't bite again.
SWOT
Strengths
- Proven track record delivering very large, high-complexity HPC/AI ASICs on TSMC's leading nodes (2nm/3nm) with advanced packaging
- Deep TSMC ecosystem relationship (Value Chain Aggregator partner) securing advanced-node and packaging access
- High profitability resilience - FY2025 net income fell only 11% despite a 38% revenue drop, on richer NRE mix
- 83% of revenue from secular AI/HPC demand — 78% North America (FY2025) - anchored to the strongest custom-silicon buyers
Weaknesses
- Severe revenue lumpiness and customer concentration — a single customer skipping a product generation drove the 38% FY2025 decline
- Structurally low blended gross margin (~26%) because turnkey/production revenue is largely foundry/OSAT pass-through
- Little disclosure of customer names, cash position, or NRE-vs-production dollar split - low transparency for outside investors
- Smaller scale and balance sheet than merchant custom-silicon rivals (Broadcom, Marvell)
Opportunities
- 2nm design wins and tape-outs opening a new multi-year production cycle
- Broadening hyperscaler/AI-accelerator customer base to reduce single-customer dependence
- Rising in-house-accelerator TAM as hyperscalers build custom chips vs buying merchant GPUs
- Advanced-packaging (CoWoS-class) content growth per design as die sizes and chiplet counts rise
Threats
- US export controls constraining advanced-node business tied to Chinese HPC/AI customers
- Competition from far larger Broadcom and Marvell (and TSMC-affiliated GUC) for the same hyperscaler custom-silicon sockets
- TSMC advanced-packaging (CoWoS) capacity allocation as a hard throughput ceiling
- Customer insourcing of design or shifting a program to a rival house - high revenue-at-risk per account
- Rich valuation (~$11B on $992M FY2025 revenue) leaves little room for a delayed ramp
Moats, dependencies & bottlenecks
Moats
Few design houses can reliably tape out reticle-scale AI accelerators on the newest node with advanced packaging; capability is hard-won but replicable by larger rivals.
VCA-level relationship secures capacity and PDK access, but the same channel is open to GUC and the merchant vendors.
High per-program Once a chip is in production, re-spinning it elsewhere is costly and slow - but the moat is per-program, not company-wide, so it evaporates at each new generation.
Accumulated blocks/methodology speed the next design; not proprietary enough to lock competitors out.
Dependencies
Supplier / manufacturing Sole leading-edge foundry path; wafer and especially advanced-packaging capacity allocation directly gate Alchip's production revenue.
Customer concentration A key customer skipping a product generation caused the FY2025 revenue collapse; names undisclosed, concentration high (78% North America FY2025).
Design flow and foundation IP depend on the EDA duopoly and Arm; cost and license terms flow through.
Turnkey production requires outsourced packaging/test capacity beyond TSMC.
Advanced-node designs for China-linked HPC/AI customers are restricted; policy shifts can remove demand overnight.
Advantages
- Pure-play leverage to leading-node AI/HPC custom silicon (83% AI/HPC, 78% North America FY2025)
- Demonstrated profit resilience through a revenue trough (FY2025 net income -11% vs revenue -38%)
- Scarce 2nm/3nm reticle-scale ASIC execution capability
- Asset-light fabless model - high returns on capital when volume is present
Weaknesses
- Extreme revenue lumpiness and single-customer fragility
- Low blended gross margin from production pass-through
- Thin public disclosure (customers, cash, revenue mix)
- Sub-scale balance sheet versus Broadcom/Marvell in competing for the largest programs
Bottlenecks
- TSMC CoWoS / advanced-packaging capacity allocation as a hard ceiling on production ramp
- Customer product-generation timing — revenue is gated by individual customers' silicon cadence, creating air-pockets
- Advanced-node design-engineering talent (2nm/3nm) scarcity
- Concentration risk: throughput and revenue tied to a handful of large programs
Top signals & trends
Top signals
Management-stated cadence; trough is Q1 2026, visible re-acceleration.
Seeds the next production generation and signals continued design-win flow.
Quantifies the concentration fragility; unresolved structurally.
Confirms design-side pricing power; blended margin will fall as production mixes in.
Sell-side expects a strong recovery - but sets a high bar the ramp must clear; stock traded ~NT$4,215 in early Jul, below the target.
Trends
Expands the custom-ASIC TAM Alchip serves; also the arena where Broadcom/Marvell compete hardest.
Raises design complexity and content per program, favoring specialist houses - but concentrates dependence on TSMC packaging.
Structurally removes/constrains a slice of prior HPC demand.
Underpins the H2-2026 recovery thesis and long-term demand for leading-node ASICs.
Grows pass-through production revenue but pressures blended margin and depends on capacity.
Ecosystem & competitor graph
Suppliers feed the company; customers pull from it. Line thickness shows the strength of each tie (supply-chain dependency, customer earnings contribution). Hover to isolate a tie.
Leading-edge foundry (2nm/3nm) and CoWoS-class advanced packaging; the critical manufacturing dependency.
OSAT assembly/test partner for turnkey production.
EDA tools and foundation IP for advanced-node design.
EDA tools and IP; the other half of the design-flow duopoly.
CPU/interconnect IP frequently integrated into HPC ASIC designs.
North American hyperscalers / AI-accelerator firms (undisclosed) 78% of FY2025 revenue is North America and 83% AI/HPC; specific customer names are not publicly disclosed, and concentration is high - a single customer's product cadence drives the revenue swings. (Q1 2026 geographic mix skewed differently - North America 23%, Asia Pacific 47% - on NRE-timing, not a structural shift.)
Japan ~8% of Q1 2026 revenue; historical large-die HPC ASIC engagements.
Prior HPC exposure now limited by US export controls; context only, not a buy/own framing.
Dominant merchant custom-AI-ASIC vendor (Google TPU, Meta accelerators); vastly larger scale and balance sheet.
Major custom-silicon supplier to hyperscalers (AWS, Microsoft programs); direct competitor for the largest sockets.
TSMC-affiliated Taiwanese ASIC design-services house - the most direct like-for-like rival with privileged TSMC access.
Japanese custom SoC/ASIC design-services firm competing on advanced-node designs.
Taiwanese ASIC/IP design-services house; competes on mid/advanced-node ASICs.
Runs a custom-ASIC business (e.g. hyperscaler AI programs) alongside its merchant SoC franchise.