Andes Technology
IP licensing + royalty: upfront license fees for CPU-core IP (~67% of FY25 revenue), per-unit royalties on shipped SoCs (~21%), and maintenance/services. RISC-V mix is still license-heavy (~92% license / ~9% royalty); management expects royalty to overtake license revenue around 2027 as licensed cores reach volume production. Mix percentages are company-reported and not independently audited here.
Earnings, margins, COGS & capex
A ~99%-gross-margin IP licensor whose reported profitability collapsed into losses because it is front-loading R&D on next-gen high-end/AI-datacenter cores (AX45MPV/AX46MPV) ahead of the royalty inflection. Revenue grew ~7% to NT$1.48B in FY2025 but MISSED consensus by ~22% (Simply Wall St) as growth decelerated hard from +31% in FY2024, and the bottom line swung from a razor-thin FY2024 profit (EPS +NT$0.04) to a NT$415.3M FY2025 loss (EPS -NT$8.20), deepening in Q1 FY2026. The bet: today's license wins become tomorrow's per-unit royalties as cumulative AndesCore SoC shipments passed 20B (Q2 2026) and datacenter designs tape out.
Income statement — where each revenue dollar goes
% of revenueOf every $1 of revenue, ~1¢ is cost of goods and ~0¢ operating expense, leaving ~99¢ of operating profit (~-28¢ net).
Revenue trend
Margins
stable/very high — structural to IP model
deteriorating — R&D ramp
swung from ~breakeven FY2024 (EPS +NT$0.04) to loss
COGS structure
Negligible — IP licensing carries almost no cost of goods (gross margin ~99%). The 'cost' base is operating expense, dominated by R&D headcount and EDA/tooling for advanced-node CPU and vector-processor development; SG&A secondary.
Capex
Minimal — fabless; no manufacturing or property-heavy capex. Value creation is expensed R&D, not capitalized capex, so reported capex intensity is near-zero while cash burn shows up in operating losses.
Latest earnings
FY2025 revenue MISSED analyst consensus by ~22% and EPS also came in below expectations (Simply Wall St); Q1 FY2026 top-line grew +20% but losses deepened on continued R&D investment
Management frames FY2026 as an investment year; sell-side models project ~25-30%/yr revenue growth ahead with the royalty inflection expected around 2027. No hard company revenue guidance number confirmed in sources.
- Cumulative AndesCore SoC shipments
- >20 billion units (Q2 2026)
- RISC-V license/royalty mix
- ~92% license / ~9% royalty (company-reported)
- Overall revenue mix
- ~67% license / ~21% royalty / ~12% maintenance+other (company-reported)
- Gross margin
- ~99%
Growth drivers
- RISC-V adoption S-curve — open ISA displacing Arm/x86 in embedded, MCU, and increasingly AI accelerators; cumulative AndesCore-powered SoCs surpassed 20 billion units (Q2 2026, announced Jun 24 2026), up from ~14B in late 2023
- AI-datacenter vector processors — AX45MPV / AX46MPV licensed by Rain AI and d-Matrix (Raptor inference); first AX46MPV customer tape-out delivered for TSMC (Dec 2025) with additional tape-outs scheduled through 2026
- License-to-royalty flip — royalty share expected to overtake license revenue ~2027 as design wins reach volume, raising recurring high-margin revenue
- New master-licensing / foundry agreements and long-run customers renewing/expanding (Sequans A25MP/N25F, 2025)
- Custom-extension / vector (RVV) demand for edge-AI and IoT SoCs
Bull & bear
A scarce, near-100%-gross-margin RISC-V IP leader sitting on a royalty inflection: heavy R&D losses today are the cost of capturing AI-datacenter design wins whose per-unit royalties compound at ~99% margin from ~2027 onward.
- RISC-V is early on an adoption S-curve; Andes is one of two-to-three credible pure-play leaders with >20B shipped SoCs of real production proof
- AI-datacenter beachhead is live and named — d-Matrix (AX46MPV for its Raptor inference architecture) and Rain AI (AX45MPV); first AX46MPV customer tape-out already delivered for TSMC
- License-to-royalty flip (~2027) would convert a lumpy license business into a recurring, near-100%-gross-margin royalty annuity — operating leverage is large if volumes come
- Asset-light model: no fabs, no capex; once R&D scales revenue, incremental margins are exceptional
- Strategic scarcity — a listed RISC-V pure-play is a rare public vehicle for the theme; ecosystem centrality (RISC-V International founding member) is hard to replicate
A sub-scale (~$47M revenue) IP house burning cash (NT$415.3M FY2025 loss, EPS -NT$8.20) at ~7x sales, whose FY2025 revenue missed consensus by ~22%, betting on a royalty inflection that is perpetually '~2 years out' while Arm's moat and better-funded RISC-V rivals crowd the same datacenter dream.
- Valuation (~$338M cap on ~$47M revenue, ~7x sales) prices in a royalty ramp that has not yet materialized — losses are deepening, not narrowing (Q1 FY2026 loss widened ~45% YoY)
- FY2025 top line missed consensus by ~22% and growth halved-plus (from +31% to +7%) — the near-term trajectory undershot, not just the profit line
- The AI-datacenter wins are early-stage tape-outs, not volume royalties; conversion is uncertain and could slip past 2027
- Competitive squeeze from SiFive, Tenstorrent, Ventana and EDA-backed ARC/Tensilica pressures license pricing exactly as Andes needs to invest more
- Small revenue base means a single delayed/lost marquee license materially dents the year; Asia-linked foundry/licensee exposure adds geopolitical tail risk
What it is worth
Comps (EV/Sales vs IP-licensing peers) + reverse-DCF sanity. At ~$338M market cap (~NT$10.48B) on ~$47M TTM revenue, Andes trades ~7x sales while loss-making — a growth/optionality multiple, not an earnings multiple. Peer set: Arm (ARM, dominant profitable IP name at a far higher sales multiple), Synopsys (SNPS) / Cadence (CDNS) (EDA+IP, profitable, lower sales multiples), plus private RISC-V pure-plays (SiFive, Tenstorrent, Ventana) with no public marks.
Design-win-to-royalty conversion stalls, losses persist, competition compresses pricing — multiple de-rates toward small-cap loss-maker levels (well below current cap)
Steady ~20-28% revenue growth, gradual royalty mix-up, break-even pushed toward/after 2027 — multiple roughly sustained as optionality plays out; ~$340-450M range
Datacenter/AI licensees (d-Matrix, Rain AI, follow-ons) reach volume; royalty overtakes license by ~2027, revenue compounds ~30%+ and margins swing positive — re-rates well above current cap on the royalty annuity
The ~7x sales multiple only makes sense if the license-to-royalty flip (~2027) and AI-datacenter design wins convert to a durable, high-margin royalty ramp. Reverse-DCF read: today's price effectively requires sustained ~25-30%+ revenue growth and a swing to profitability as royalties scale on near-100% gross margin. The FY2025 consensus miss (-22%) and widening Q1 FY2026 loss cut against that; if datacenter wins reach volume the asset-light model justifies a premium, if conversion slips the multiple compresses toward loss-making-small-cap levels.
SWOT
Strengths
- Top-tier RISC-V IP pure-play with deep, proven core portfolio (AndesCore N/A/AX series) and >20B cumulative shipped SoCs — real production track record, not slideware
- Founding Premier Member of RISC-V International — standards influence and ecosystem centrality
- ~99% gross margin, asset-light fabless model — every incremental royalty dollar is nearly pure profit at scale
- Established, multi-year license contracts and long-standing customers (e.g. Sequans) create recurring maintenance + future royalty streams
Weaknesses
- Small absolute scale (~$47M revenue) and now loss-making (NT$415.3M FY2025 loss) — thin buffer against R&D over-runs or a licensing air-pocket
- FY2025 revenue missed consensus by ~22% and growth decelerated from +31% to +7% — top-line lumpiness is real, not theoretical
- License-heavy revenue still awaiting the royalty inflection — cash flow depends on deal timing
- Concentration on a handful of marquee AI-datacenter design wins that have not yet reached volume royalties
- Sub-scale in software/tooling ecosystem versus Arm's decades-deep toolchain and OS/support moat
Opportunities
- AI-datacenter inference accelerators (d-Matrix, Rain AI) as a new, higher-value licensing frontier beyond embedded/MCU
- Royalty overtaking license revenue (~2027) — structurally lifts margin quality and recurring revenue
- RISC-V share gains against Arm/x86 amid ISA-royalty-cost and geopolitical diversification pressure
- Custom vector/RVV extensions and domain-specific cores for edge AI, automotive, IoT
Threats
- Arm's incumbency, toolchain depth, and aggressive RISC-V-defense; x86 in datacenter
- Well-funded RISC-V rivals (SiFive, Tenstorrent, Ventana) and EDA giants' processor IP (Synopsys ARC, Cadence Tensilica) compressing pricing
- Design-win-to-royalty conversion risk — a licensed core that never ships in volume yields no royalty
- Customer/geographic concentration and Asia/China export-control and cross-strait geopolitical volatility
Moats, dependencies & bottlenecks
Moats
>20B cumulative AndesCore-powered SoCs — production credibility competitors can't fabricate overnight
Moderate-Strong Once a customer's SoC and software stack are built on AndesCore, re-porting to another ISA/core is costly; drives multi-year royalty tails and long-standing relationships (Sequans)
Founding Premier Member of RISC-V International; toolchain, partners, and standards influence
RVV vector cores and custom-extension know-how for edge-AI/datacenter workloads
Dependencies
Foundry (for customers' silicon) Andes is fabless; its customers tape out AndesCore designs at TSMC — ecosystem dependency, not a direct COGS input
Design tools / verification flows Advanced-node CPU/vector IP development depends on third-party EDA and formal-verification flows
Standard governance Business rests on the RISC-V ISA remaining open and widely adopted; Andes helps steer it as a premier member
Customer / royalty pipeline Future royalty upside is concentrated in a few early design wins that must reach volume production
Customer/geography Export controls and cross-strait geopolitics can disrupt Asia/China-exposed revenue
Advantages
- Near-100% gross margin, fabless, zero-capex economics
- Listed RISC-V pure-play with production-scale shipment proof (>20B SoCs)
- Named AI-datacenter design wins (d-Matrix, Rain AI) validating the high-value expansion
- Sticky, multi-year, recurring-royalty customer relationships
Weaknesses
- Sub-scale revenue and deepening losses; cash burn ahead of royalty inflection
- Revenue lumpiness and a FY2025 consensus miss; reliance on license-deal timing
- Concentration on a few unproven-at-volume marquee wins
- Ecosystem/toolchain depth gap versus Arm; pricing pressure from better-funded rivals
Bottlenecks
- License-to-royalty conversion timing — royalties lag design wins by years and gate cash-flow break-even
- R&D capacity/talent to fund multiple advanced-node + AI-datacenter core programs simultaneously on a small revenue base
- Software/toolchain maturity for high-end (datacenter) sockets versus Arm's incumbent ecosystem
- Customer volume ramp dependent on end-market SoC success outside Andes's control
Top signals & trends
Top signals
The single most important structural signal; targeted ~2027
First TSMC customer tape-out Dec 2025; watch for follow-on licensees converting
Bearish (near-term) · Q1 FY2026 loss widened ~45% YoY — burn must eventually narrow
Expands addressable royalty base
Incumbent defense can slow high-value adoption
Trends
Open ISA momentum in embedded and, increasingly, AI accelerators; multi-year secular tailwind
Vector/RVV cores (AX45MPV/AX46MPV) address a new, higher-value TAM
Industry-wide shift lifts recurring high-margin revenue
Drives ISA diversification (tailwind) but adds Asia/China-exposure risk (headwind)
Synopsys ARC / Cadence Tensilica pressure standalone IP pricing
Ecosystem & competitor graph
Suppliers feed the company; customers pull from it. Line thickness shows the strength of each tie (supply-chain dependency, customer earnings contribution). Hover to isolate a tie.
EDA tools + verification flows for core development
EDA design/verification tooling
Formal-verification / safety-collateral flows (unit of Siemens AG, ETR:SIE)
Foundry where Andes-based customer SoCs tape out (AX46MPV first customer tape-out)
ISA standards body; Andes is a founding premier member
Selected AndesCore AX46MPV for its Raptor generative-AI datacenter inference architecture (private)
Licensed AX45MPV RISC-V vector core for compute-in-memory ML hardware (private)
Long-standing customer; licensed A25MP & N25F cores for next-gen IoT chipsets (2025)
>20B cumulative AndesCore-powered SoCs across IoT, storage, wireless, automotive customers
Dominant CPU-IP incumbent; the primary alternative ISA and toolchain Andes displaces at the low end and challenges at the high end
US RISC-V pure-play, often cited as segment share leader; closest direct competitor (private, well-funded)
EDA giant with embedded processor IP and RISC-V support; bundles IP with tools
EDA giant with Tensilica DSP/processor IP; overlaps in edge-AI/vector sockets
US RISC-V + AI-accelerator entrant (private, led by Jim Keller); high-end datacenter overlap
US RISC-V datacenter-class CPU chiplets (private); competes for the datacenter dream
Legacy ISA firm pivoted to RISC-V (private); competes in embedded/automotive
European customizable RISC-V IP (private)
UK IP house with a RISC-V CPU line (private)
Mainland-China RISC-V core team; a real competitor in Asia — named for context only, not a buy/own call