d-Matrix
Fabless silicon + full-stack platform: sells Corsair PCIe accelerator cards, SquadRack/rack-scale reference systems, JetStream networking, and Aviator software to hyperscale, enterprise, neocloud, and sovereign customers; manufactures via TSMC (with Alchip on ASIC/packaging). Pre-revenue-scale, venture-funded.
Only the Series C valuation (~$2B) is officially disclosed; the Series A ($44M) and Series B ($110M) raise amounts are confirmed but their round valuations were not published — the 0.2 and 0.55 figures are conservative estimates for trend shape only, not disclosed marks. Cumulative equity raised ~$450M across the three rounds.
Earnings, margins, COGS & capex
d-Matrix does not publicly disclose revenue, margins, or cash. It has raised ~$450M in total equity across three rounds (Series A/B and the $275M Series C at a ~$2B valuation in Nov 2025). The Corsair inference platform entered full/volume production on 2026-06-09, marking the transition from pre-revenue/design-win phase toward commercial shipments to priority hyperscalers, neoclouds, and frontier AI labs. Treat any revenue number as unverified until a filing or the company discloses it.
Revenue trend
Margins
n/a — early commercial ramp; fabless hardware margins typically below software but above foundry
assumed negative during scale-up
COGS structure
not disclosed. Cost structure driven by TSMC N6 (6nm) wafer + advanced packaging for Corsair, chiplet assembly, DIMC SRAM die area, LPDDR5 off-chip capacity memory, board/system BOM, and networking (JetStream); the next-gen Raptor adds 3D-stacked DRAM (3DIMC) co-developed with Alchip. Raptor's process node has not been officially disclosed.
Capex
not disclosed. Fabless model — no owned fabs; principal 'capital' outlays are NRE/tape-out and mask costs, test silicon (Pavehawk), and working-capital inventory ahead of volume shipments.
Latest earnings
n/a
No formal guidance. Company messaging: Corsair in full/volume production as of Jun 2026; capital to fund global expansion and multiple large-scale deployments.
- Total raised
- ~$450M (through Series C)
- Series C
- $275M, Nov 2025, ~$2B valuation
- Founded / HQ
- 2019, Santa Clara CA; CEO/founder Sid Sheth, CTO Sudeep Bhoja
- Headcount
- 250+ employees; design centers/offices in Toronto, Sydney, Bangalore, Belgrade, Seattle
- Corsair claim (per-rack)
- ~30,000 tok/s on Llama3-70B at ~2ms/token latency; ~150 TB/s on-chip bandwidth
- Corsair claim (per-card)
- 2400 TFLOPs 8-bit peak; 2GB integrated SRAM Performance Memory + up to 256GB off-chip LPDDR5 Capacity Memory
- Process
- Corsair on TSMC N6 (6nm); next-gen Raptor node not officially disclosed
Growth drivers
- Secular shift of AI spend from training to inference — CEO frames inference as a '$1T market in the making'
- Corsair full/volume production (Jun 2026) converting design wins into shipments to priority hyperscale/neocloud/frontier-lab buyers
- Energy/TCO angle — per independent Gimlet Labs testing, Corsair paired with an Nvidia GPU is claimed up to 10x faster, ~3x cheaper, and up to ~5x more energy-efficient than a standalone GPU; a single Corsair C8 card is claimed at up to ~9x the throughput of an Nvidia H100
- Sovereign-AI demand (QIA, EDBI, Temasek as investors align with a sovereign customer pipeline)
- SquadRack rack-scale reference architecture with Arista, Broadcom, Supermicro lowering integration friction
- Roadmap to Raptor + 3DIMC (3D-stacked DRAM) targeting the HBM 'memory wall' with Alchip collaboration
Bull & bear
If inference is the larger, longer-duration market and DIMC delivers a real perf-per-watt and latency edge, d-Matrix is an early, well-backed pure-play riding that shift with a credible roadmap and marquee investors — a high-optionality private position ahead of a potential IPO.
- Inference is a structurally larger deployment market than training; a focused pure-play with a genuine architecture edge can capture meaningful share even against Nvidia
- DIMC/SRAM bandwidth (~150 TB/s on-chip) targets the exact bottleneck that limits GPU inference efficiency on small-batch/low-latency serving
- Full-stack + reference-rack (SquadRack) strategy and tier-1 integration partners de-risk enterprise/sovereign adoption
- Marquee cap table (Microsoft M12, Temasek, QIA, EDBI) provides capital, credibility, and a sovereign/hyperscaler pipeline
- Corsair reaching full production (Jun 2026) is the key de-risking milestone, with independent Gimlet Labs testing backing the perf/energy story; Raptor + 3DIMC offers a second act against HBM
- ~$2B entry valuation is modest relative to public AI-infra comps if commercial traction materializes
d-Matrix is a pre-scale, unprofitable challenger with undisclosed revenue, taking on the strongest moat in tech (Nvidia/CUDA) plus its own hyperscaler backers' in-house chips — with an SRAM-heavy design whose large-model economics and a still-unproven 3D-DRAM roadmap are the whole thesis.
- No disclosed revenue at scale; the commercial ramp has barely begun and design wins do not guarantee volume
- CUDA software lock-in and Nvidia's roadmap velocity have defeated better-funded challengers before
- SRAM-centric capacity limits may make large-model / long-context serving economically unattractive vs HBM systems, and the headline 10x/5x figures rely on a Corsair-plus-GPU configuration rather than standalone silicon
- Its biggest strategic backer (Microsoft) and other hyperscalers are building competing in-house inference silicon, capping the merchant opportunity
- Key differentiation (3DIMC via Pavehawk/Raptor) is still test-silicon — execution and yield risk on an aggressive roadmap whose node is not yet disclosed
- Single-foundry (TSMC) dependency for advanced nodes/packaging against far larger allocation competitors; AI-capex cyclicality amplifies downside
What it is worth
Last-priced private round (no public market); cross-checked against listed AI-silicon comps qualitatively.
Stalled adoption, CUDA lock-in, hyperscaler in-house silicon, or an AI-capex pullback could force a flat/down round or strand the company as a niche vendor well below the last mark.
~$2B holds or steps up modestly as commercial shipments prove out through 2026-2027; outcome hinges on converting design wins to recurring revenue.
Successful Corsair volume ramp + independently-validated standalone TCO edge + on-time 3DIMC could support a substantial step-up at the next round/IPO, re-rating toward public AI-infra multiples.
Anchored to the Nov 2025 Series C: ~$2B post-money on $275M raised (~$450M cumulative). No public price or trading multiple exists; revenue undisclosed so a revenue multiple cannot be computed. Value is optionality on the inference-market thesis and execution of the Corsair ramp + Raptor/3DIMC roadmap, not current cash flows. Not financial advice; private/pre-IPO — illiquid, and secondaries (if any) are not verified here.
SWOT
Strengths
- Differentiated digital in-memory compute (DIMC) architecture attacking the memory-bandwidth bottleneck rather than brute-force FLOPS
- Strategic backing — Microsoft's M12, Temasek, QIA, EDBI, Mirae Asset — capital plus sovereign/hyperscaler channel signal
- Full-stack delivery (silicon + JetStream networking + Aviator software + SquadRack systems) lowers customer adoption risk
- Focused purely on inference — a cleaner wedge than trying to beat Nvidia at training
- Independent Gimlet Labs benchmarking lends third-party support to the perf/energy claims, plus credible ecosystem integration partners (Arista, Broadcom, Supermicro), foundry (TSMC), and Alchip for 3D DRAM
Weaknesses
- No disclosed revenue at scale — commercial ramp only began (Corsair full production Jun 2026) — execution unproven
- SRAM-centric design trades capacity for bandwidth — large-model/long-context economics vs HBM systems remain to be proven at scale
- Tiny relative to Nvidia's software moat (CUDA) and installed base; customers must port/optimize to Aviator
- Heavily dependent on a single foundry (TSMC) and on a nascent 3DIMC/3D-DRAM roadmap still at test-silicon (Pavehawk) stage
- Capital-intensive multi-generation roadmap against far better-funded incumbents and hyperscaler in-house silicon
Opportunities
- Inference TAM expanding faster than training as models get deployed at scale
- Energy-constrained data centers create demand for perf-per-watt alternatives to GPUs
- Sovereign-AI build-outs (Gulf, SE Asia) seeking non-Nvidia supply diversification
- 3DIMC/Raptor roadmap could leapfrog HBM4-based systems on latency and energy if it ships on time (claimed up to 10x faster than HBM4)
- Potential future IPO or strategic partnership given oversubscribed Series C demand
Threats
- Nvidia's cadence (Blackwell/Rubin), CUDA lock-in, and aggressive inference positioning
- Hyperscaler in-house inference silicon (Google TPU, AWS Inferentia/Trainium, Microsoft Maia) shrinking the merchant-silicon opening — including at its own backer Microsoft
- Well-funded merchant rivals (Groq, Cerebras, SambaNova, AMD, Etched) chasing the same inference wedge
- Foundry capacity/allocation competition with much larger buyers for TSMC advanced nodes/packaging
- AI-capex cycle risk — a spending pullback would hit an unprofitable pre-scale vendor hardest
Moats, dependencies & bottlenecks
Moats
Digital in-memory compute is genuinely differentiated, but architecture alone is replicable and must be defended by shipping and software.
Needed to counter CUDA but nowhere near CUDA's maturity or ecosystem; a chicken-and-egg adoption problem.
Microsoft M12, Temasek, QIA, EDBI plus Arista/Broadcom/Supermicro/TSMC/Alchip give channel and supply credibility.
The 10x speed / ~3x cost / ~5x energy edge (independently tested by Gimlet Labs) is measured for Corsair paired with a GPU vs GPU-only; it must still survive broad, independent production workloads at volume.
Dependencies
Foundry / advanced packaging Corsair on N6 (6nm); allocation and packaging capacity compete with far larger buyers.
Design/ASIC + 3D DRAM collaboration Partner for the claimed world's-first 3D-stacked DRAM (3DIMC) roadmap central to Raptor differentiation.
Investor + prospective customer Backer and potential anchor customer that also builds its own Maia inference silicon — alignment could reverse.
Pre-profit; future rounds/IPO depend on AI-capex sentiment staying constructive.
3D-DRAM roadmap ties future performance to advanced memory supply and yields.
Advantages
- Pure-play inference focus — no distraction fighting Nvidia on training
- Architecture aimed at the real bottleneck (memory bandwidth), not just FLOPS
- Rack-scale, full-stack delivery with tier-1 integration partners
- Strong sovereign/hyperscaler-aligned cap table and capital runway (~$450M raised)
- Early-mover on 3D-stacked DRAM for inference
Weaknesses
- No disclosed revenue/margins; commercial scale unproven
- No software moat comparable to CUDA
- Single-foundry and single-3D-DRAM-partner concentration
- Backers building competing in-house silicon
- Capital-intensive roadmap vs better-funded incumbents
Bottlenecks
- Software ecosystem maturity vs CUDA — porting/optimization friction for customers
- SRAM capacity ceiling for large-model / long-context inference economics
- 3DIMC/3D-DRAM still at test-silicon (Pavehawk) — must reach production yield on schedule
- TSMC advanced-node and packaging allocation against much larger competitors
- Proving vendor performance claims on independent, standalone production workloads at volume
Top signals & trends
Top signals
The key transition from design-win to commercial shipments to priority hyperscalers, neoclouds, and frontier AI labs.
Co-led by BullhoundCapital, Triatomic Capital, and Temasek; adds QIA + EDBI, with follow-on from M12 and Mirae Asset; ~$450M total raised.
Signals a differentiated Raptor roadmap (claimed up to 10x faster than HBM4), but still test-silicon (Pavehawk).
Independence + IPO optionality vs near-term liquidity.
Backer-as-competitor tension in the merchant inference market.
Trends
Directly expands d-Matrix's addressable market.
Elevates perf-per-watt alternatives to GPUs.
Compresses the merchant-silicon opening at the largest buyers.
Incumbent defends the exact wedge d-Matrix targets.
Aligns with QIA/EDBI/Temasek backing and non-Nvidia demand.
d-Matrix positioned early with 3DIMC if it ships.
Ecosystem & competitor graph
Suppliers feed the company; customers pull from it. Line thickness shows the strength of each tie (supply-chain dependency, customer earnings contribution). Hover to isolate a tie.
Foundry for Corsair (N6/6nm) plus advanced packaging.
ASIC/design partner; joint 3D-stacked DRAM (3DIMC) development for Raptor.
Networking/connectivity partner in SquadRack reference architecture.
Priority buyers for volume Corsair shipments (specific names not disclosed).
Gulf / SE-Asia sovereign customers aligned with QIA/EDBI/Temasek backing.
Named as target segments; individual customers not publicly disclosed.
Dominant incumbent; CUDA moat + Blackwell/Rubin inference roadmap. The reference point d-Matrix benchmarks against.
Instinct MI-series + ROCm; the main merchant-GPU alternative pushing inference TCO.
LPU deterministic low-latency inference; direct architectural rival for fast token serving.
Wafer-scale WSE; fast-inference cloud; competes for the inference-speed narrative.
Reconfigurable dataflow RDU with tiered SRAM/HBM/DRAM memory for large models.
Gaudi inference accelerators positioned on price/performance.
Transformer-ASIC (Sohu) challenger on the same inference wedge.
RISC-V-based AI accelerators; emerging custom-silicon challenger.
Hyperscaler in-house inference silicon that removes the largest buyers as merchant customers.