Empyrean Technology
Licenses and subscriptions for EDA software tools (analog/mixed-signal design + verification, digital design, flat-panel/memory flows) plus IP and engineering services; state-linked (controlled by China Electronics Corporation since Dec 2024).
Earnings, margins, COGS & capex
Revenue grows steadily high-single-digits but profit has cratered: FY2025 net income CN¥60.98M (-44.3% YoY) and TTM net income turned slightly negative (-CN¥21.73M) as R&D consumed ~73% of revenue (H1 2025 R&D CN¥365M) and government subsidies shrank. The clearest tell of the subsidy dependence: FY2025 net income EXCLUDING non-recurring items (mostly government grants) was a loss of -CN¥9.8M — the operating business did not make money on its own. High-gross-margin (~89%) software economics are being fully reinvested into closing the technology gap with Synopsys/Cadence/Siemens, so reported earnings are a policy/subsidy residual, not a stable base. Rich strategic-scarcity valuation (~47x sales, forward P/E ~160) prices in localization dominance rather than current profitability.
Income statement — where each revenue dollar goes
% of revenueOf every $1 of revenue, ~11¢ is cost of goods and ~0¢ operating expense, leaving ~89¢ of operating profit (~5¢ net).
Revenue trend
Margins
stable/high
down sharply from ~9% FY2024
collapsed -91.9% YoY
operating business unprofitable on its own
elevated, rising
into loss on Q1-2026 drag
COGS structure
Low relative to revenue — EDA is licensed software, so cost of revenue is modest (support, some third-party/foundry-PDK and IP components); gross margin sits ~89% (reverified). The real 'cost' is below the gross line: R&D headcount (largest EDA R&D team in China) that eats ~two-thirds-plus of revenue.
Capex
Low; asset-light software house. No large fab/plant capex. Cash deployment skews to R&D (opex) and M&A ambitions (e.g., the attempted Xpeedic stock+cash deal) rather than fixed assets.
Latest earnings
Profit well below prior-year and consensus — a sharp miss on earnings even as revenue met modest-growth expectations
No hard FY guidance disclosed here; sell-side full-year revenue estimates ranged ~CN¥1.3-1.76B, with the low end (~CN¥1.32B) realized
- FY2025 revenue
- CN¥1.325B (+8.4%)
- FY2025 net income
- CN¥60.98M (-44.3%)
- FY2025 net income ex-non-recurring
- -CN¥9.8M (a loss without subsidies)
- R&D intensity
- ~73% of revenue
- China EDA market share
- ~6% (largest domestic, #4 global)
- Forward P/E
- ~160x (160.56)
Growth drivers
- China semiconductor-localization / self-sufficiency mandate forcing domestic fabless + IDMs off foreign EDA
- US Entity List (Dec 2024) on Empyrean cuts its own foreign-tool access but hardens domestic customer capture as a second-order effect
- Analog / mixed-signal full-flow leadership (partial 5nm) — its strongest, most defensible franchise
- New China-first full-process EDA platform for memory-chip production (Aug 2025), tapping CXMT/YMTC-class domestic memory capex
- Technical-services revenue growth (FY2025 +74.9% to ~CN¥200M) and overseas revenue (+127.5% to ~CN¥130M) diversifying the mix
- Product-matrix broadening via organic build plus M&A ('dual-track') to close the digital full-flow gap
Bull & bear
Empyrean is the default beneficiary of an irreversible, state-mandated multi-decade shift of China's chip designers onto domestic EDA — a structurally captive, growing demand base where it is the clear national champion with the only credible analog full-flow and the deepest R&D bench.
- Localization is policy, not preference: export controls + the self-sufficiency mandate convert Chinese fabless/IDM/memory customers into forced adopters, and Empyrean is first in line
- The Entity List paradoxically strengthens the domestic demand moat even as it raises Empyrean's own R&D cost
- Analog/mixed-signal (partial 5nm) is a real, defensible franchise where the node gap to foreign tools matters less than in digital
- Memory full-flow first-mover aligns with a large domestic DRAM/NAND buildout (CXMT/YMTC-class capex)
- CEC control + Big Fund backing = patient capital to sustain ~73% R&D intensity long enough to close the gap
- ~89% gross margins mean the model prints cash the moment R&D intensity normalizes
You are paying ~47x sales and a forward P/E of ~160 for a company whose profit just fell 44% (and went negative TTM), whose FY2025 profit was actually a loss once you strip out government subsidies, that still can't do full-flow digital at advanced nodes, and that just fumbled its key acquisition.
- Digital full-flow gap at leading-edge nodes is the whole game for advanced SoCs — and Empyrean doesn't have it; Synopsys/Cadence keep moving the frontier
- Earnings are a subsidy residual: FY2025 net income ex-non-recurring items was -CN¥9.8M — the operating business lost money despite ~89% gross margins
- R&D at ~73% of revenue is unsustainable-looking as a profit model for years — the catch-up is expensive and open-ended
- Xpeedic deal collapse (Jul 2025) undercuts the inorganic full-flow roll-up thesis and signals execution/integration risk
- Cut off from foreign tools/IP, it must reinvent more of the stack itself — slower and costlier
- Valuation prices dominance already achieved; any slip in growth or subsidy invites severe multiple compression
What it is worth
Multiples vs strategic-scarcity premium (context, not advice)
Advanced-node gap proves persistent, subsidies keep shrinking, and consolidation stalls (post-Xpeedic); growth decelerates and the ~47x-sales / ~160x-forward-P/E multiple compresses sharply toward domestic-software norms.
High-single-to-mid-teens revenue growth continues, profits stay subsidy-sensitive and thin (or negative ex-subsidy) for several years while the digital/advanced-node gap slowly narrows; valuation stays elevated on policy premium but is vulnerable to de-rating on any growth or subsidy wobble.
If forced domestic substitution compounds revenue at ~20-30%+ for years and R&D intensity eventually normalizes toward software-like margins, today's sales multiple could be defended by a much larger, profitable franchise; memory + analog leadership underwrite the demand.
At CN¥63.93B (~US$8.9B) on ~CN¥1.35B TTM revenue, the stock trades ~47x sales (63.93/1.35) with a forward P/E ~160x (160.56) and negative TTM EPS (-CN¥0.04) — a valuation set by the strategic-scarcity / national-champion premium and a long localization runway, not by current cash flows. FY2025 profit ex-subsidies was a loss, so trailing earnings offer no support. Sensitive to policy/subsidy continuity and to whether the digital full-flow gap closes. Mainland-China A-share (no ADR); named for context only, not a buy/own recommendation and not financial advice.
SWOT
Strengths
- Largest domestic Chinese EDA vendor and #4 globally (~6% China share) — the national champion designation carries policy and procurement weight
- Genuine analog/mixed-signal full-flow capability (partial 5nm) — not a shell; a real, competitive product line
- State backing — controlled by China Electronics Corporation (CEC, ~34% equity + board control) with China IC 'Big Fund' and Shenzhen Capital Group as investors — deep-pocketed, patient capital
- High-80s/90 gross margins (~89%) and a large, hard-to-replicate EDA R&D talent pool inside China
Weaknesses
- No complete digital full-flow at advanced nodes — digital tools cap around 7nm and lack full place-and-route/signoff coverage vs Synopsys/Cadence
- Earnings quality is poor and subsidy-dependent — net profit collapsed 44% FY2025, TTM turned negative, and FY2025 profit ex-subsidies was actually a loss
- R&D burn (~73% of revenue) means profitability is structurally thin for years as it funds the catch-up
- Cut off from foreign EDA tools/IP by the US Entity List, raising its own cost of closing the technology gap
Opportunities
- Forced substitution — every export-controlled Chinese design house is a captive prospect to migrate off Synopsys/Cadence/Siemens
- Memory-EDA first-mover (China-first full-process memory platform, Aug 2025) into a large domestic DRAM/NAND capex wave
- Consolidation of China's fragmented EDA scene into a full-flow suite via M&A (portfolio roll-up thesis)
- AI-driven chip-design demand expands the EDA TAM broadly
Threats
- Synopsys and Cadence are generations ahead at advanced nodes and iterate fast — the moving target may never be caught at leading edge
- Subsidy withdrawal / policy shifts directly hit the bottom line (already demonstrated in 2025)
- Failed Xpeedic acquisition (terminated Jul 9 2025) shows consolidation execution risk — the inorganic leg of the strategy stalled
- Valuation (~47x sales, forward P/E ~160) leaves no margin for disappointment; multiple compression risk is high
Moats, dependencies & bottlenecks
Moats
Strong (domestically) High while localization mandate persists CEC control (~34% + board) + Big Fund + Entity-List-driven forced substitution make it the default domestic EDA — a regulatory/geopolitical moat, not a pure product moat.
Moderate-Strong Real, competitive analog flow (partial 5nm) that is genuinely hard to replicate; its most defensible product asset.
EDA flows are sticky once a design team standardizes, but Empyrean is often the challenger displacing incumbents, so it benefits less than Synopsys/Cadence do.
Largest EDA R&D pool in China — a scarce-talent advantage domestically, though small vs Synopsys/Cadence globally.
Dependencies
China semiconductor-localization policy + Entity-List-driven substitution Regulatory / geopolitical demand driver The demand thesis IS the policy; a de-escalation or policy shift would soften the forced-adoption tailwind.
Subsidy reduction directly caused the 2025 profit collapse; FY2025 profit ex-subsidies was a loss — profitability is not yet organically self-sustaining.
Supplier / interoperability Tool value depends on process design kits from domestic fabs, especially as foreign-foundry access narrows.
Catch-up depends on scarce, expensive EDA R&D talent; competition for it is intense.
Supply constraint Cut off from Western tools/IP it once leaned on, raising the cost/time of building the full stack itself.
Advantages
- Largest domestic Chinese EDA vendor / national champion with policy and procurement tailwinds
- Genuine analog/mixed-signal full-flow (partial 5nm) leadership
- China-first full-process memory-chip EDA platform (Aug 2025 first-mover)
- CEC + Big Fund state backing = patient, deep capital
- ~89% software gross margins with large operating leverage if R&D intensity ever normalizes
Weaknesses
- Digital full-flow and advanced-node gap vs Synopsys/Cadence/Siemens
- Subsidy-dependent, collapsing earnings (net profit -44% FY2025, negative TTM, loss ex-subsidy)
- Unsustainably high R&D burn for the current revenue base
- M&A execution risk exposed by the failed Xpeedic deal
- Extreme valuation (~47x sales, ~160x forward P/E) with little error margin
Bottlenecks
- No complete digital full-flow at advanced nodes (caps ~7nm — lacks full place-and-route/signoff) — the biggest technical gap
- Advanced-node (sub-7nm) support lags foreign leaders by generations
- Profitability throttled by ~73% R&D intensity and subsidy dependence (loss-making ex-subsidy)
- Inorganic portfolio completion stalled after the terminated Xpeedic acquisition
- Entity-List isolation slows access to leading-edge tool/IP building blocks
Top signals & trends
Top signals
bullish (demand) · Structural, multi-year forced-substitution tailwind for the domestic champion.
Hurts Empyrean's own tool/IP access but hardens domestic customer capture — net demand-positive, cost-negative.
bearish (earnings quality) · Shows the business is not yet organically profitable at scale.
bearish (strategy) · Inorganic full-flow consolidation leg stalled on terms.
bearish (valuation) · Prices dominance already; high multiple-compression risk.
bullish (product) · First-mover into domestic memory capex cycle.
Trends
high positive on domestic demand, negative on tool access · The defining structural force; converts controls into a captive domestic customer base.
Expands EDA TAM broadly, including domestically.
Feeds the new memory-EDA platform.
Keeps R&D intensity high and the catch-up expensive/open-ended.
Ecosystem & competitor graph
Suppliers feed the company; customers pull from it. Line thickness shows the strength of each tie (supply-chain dependency, customer earnings contribution). Hover to isolate a tie.
SMIC (SSE:688981 / HKEX:0981) and Hua Hong (SSE:688347 / HKEX:1347) supply the process design kits Empyrean's tools calibrate to — context only.
Third-party IP, algorithms, and compute; access to Western components constrained by Entity List.
Scarce specialized engineers; the key input to the catch-up.
Broad domestic SoC/analog designers migrating off foreign EDA under localization pressure.
CXMT / YMTC-class DRAM/NAND makers (private) targeted by the new memory-EDA platform — context only.
SMIC / Hua Hong and other IDMs using analog/mixed-signal and manufacturing flows.
Global #1 EDA; full-flow leader across all nodes; the primary tool Empyrean's customers are being pushed off.
Global #2 EDA; especially strong in digital/analog and system design; generations ahead at leading edge.
Global #3 EDA; strong verification/DFT/PCB; part of the Western trio Empyrean substitutes against.
Domestic EDA peer focused on device modeling / manufacturing EDA and fast-SPICE; direct China rival.
Domestic EDA + test-chip / yield-analysis specialist; adjacent China competitor.
Private Chinese EDA startup targeting digital verification / full-flow; well-funded domestic challenger (no public ticker).